📄 _primary.vhd
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library verilog;use verilog.vl_types.all;entity ALUComb is port( ALUCombResult : out vl_logic_vector(31 downto 0); out_Carry : out vl_logic; out_Zero : out vl_logic; out_Neg : out vl_logic; out_Overflow : out vl_logic; ALUComb_ALUType : in vl_logic_vector(7 downto 0); ALUComb_LeftOperand: in vl_logic_vector(31 downto 0); ALUComb_RightOperand: in vl_logic_vector(31 downto 0); ALUComb_ThirdOperand: in vl_logic_vector(31 downto 0); ALUComb_RightOperandShiftType: in vl_logic_vector(1 downto 0); ALUComb_RightOperandShiftCount: in vl_logic_vector(4 downto 0); ALUComb_ShiftCountInReg: in vl_logic; ALUComb_ShiftCountHigh3Bit: in vl_logic_vector(2 downto 0); ALUComb_Operand2IsReg: in vl_logic; in_Carry : in vl_logic; in_Overflow : in vl_logic; in_Neg : in vl_logic; in_Zero : in vl_logic );end ALUComb;
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