srlc32e_macro.v

本人正在学习vhdl语言

//
// Module: 	SRLC32E_MACRO
//
// Description: SelectShiftRegister-II macro
//		32 bit Shift Register with Carry and Clock Enable
//		Use template "SRLC16E.v"
//
// Device: 	VIRTEX-II Family
//
// Date:	SAK / 04-17-2000 - XILINX
//
// Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 2000 Xilinx, Inc.  All rights reserved.
//-----------------------------------------------------------------------------------------------------

module SRLC32E_MACRO (D, CE, CLK, A0, A1, A2, A3, A4, Q, Q32);

input D;
input CLK;
input CE;
input A0, A1, A2, A3, A4;

output Q;
output Q32;

wire Q15;
wire Q_MUX_00_15;
wire Q_MUX_16_31;



//Instantiate 16-bit shift registers: SRLC16E//
   SRLC16E U_SRLC16E_0 ( .D(D),
			 .A0(A0),
                         .A1(A1),
                         .A2(A2),
                         .A3(A3),
                         .CLK(CLK),
                         .CE(CE),
                         .Q(Q_MUX_00_15),
                         .Q15(Q15)
		       );

   SRLC16E U_SRLC16E_1 ( .D(Q15),
                         .A0(A0),
                         .A1(A1),
                         .A2(A2),
                         .A3(A3),
                         .CLK(CLK),
                         .CE(CE),
                         .Q(Q_MUX_16_31),
                         .Q15(Q32) 
			);

//Instantiate MUXF5 for Addressable output//
    MUXF5_L      U_MUXF5_L ( .O(Q),
                             .I0(Q_MUX_00_15),
                             .I1(Q_MUX_16_31),
                             .S(A4)
			   );


endmodule