代码搜索：Carry
找到约 8,060 项符合「Carry」的源代码
代码结果 8,060
www.eeworm.com/read/310741/13644727
vhd count24.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count24 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/306208/13749254
vhd count60.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count60 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/306208/13749262
vhd count24.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count24 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/487908/6501835
txt 加法器：generate语句的应用.txt
-- n-bit Adder using the Generate Statement
-- download from: www.fpga.com.cn & www.pld.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY addn IS
GENERIC(n : POSITIVE := 3); --no.
www.eeworm.com/read/482306/6622565
v adder16.v
module adder16(a,b,c,d,carry_in,sum,carry_out);
input [15:0] a,b,c,d;
input carry_in;
output [15:0] sum;
output carry_out;
wire [15:0] a,b,c,d;
wire carry_in;
reg [15:0] sum;
wire carry_out;
www.eeworm.com/read/263314/11367749
txt adder_nbit_generate.txt
-- n-bit Adder using the Generate Statement
-- download from: www.fpga.com.cn & www.pld.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY addn IS
GENERIC(n : POSITIVE := 3); --no.
www.eeworm.com/read/157209/11730125
txt 加法器：generate语句的应用.txt
-- n-bit Adder using the Generate Statement
-- download from: www.fpga.com.cn & www.pld.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY addn IS
GENERIC(n : POSITIVE := 3); --no.
www.eeworm.com/read/149929/12330995
vhd addn.vhd
-- n-bit Adder using the Generate Statement
-- download from: www.fpga.com.cn & www.pld.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY addn IS
GENERIC(n : POSITIVE := 3); -
www.eeworm.com/read/149607/12362869
txt adder_nbit_generate.txt
-- n-bit Adder using the Generate Statement
-- download from: www.fpga.com.cn & www.pld.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY addn IS
GENERIC(n : POSITIVE := 3); --no.
www.eeworm.com/read/232223/14203306
v m3s056ct.v
//******************************************************************* //
//IMPORTANT NOTICE //
//================