adder16.v

本程序是在一位全加器的基础上设计一个16位的加法器,用Verilog HDL语言描述.

module adder16(a,b,c,d,carry_in,sum,carry_out);
input [15:0] a,b,c,d;
input carry_in;
output [15:0] sum;
output carry_out;
wire [15:0] a,b,c,d;
wire carry_in;
reg [15:0] sum;
wire carry_out;
wire carry_out0;
wire carry_out1;
wire carry_out2;
wire carry_out3;
wire carry_out4;
wire carry_out5;
wire carry_out6;
wire carry_out7;
wire carry_out8;
wire carry_out9;
wire carry_out10;
wire carry_out11;
wire carry_out12;
wire carry_out13;
wire carry_out14;
wire carry_out15;
myadder adder0(.a(a[0]),.b(b[0]),.c(c[0]),.d(d[0]),.carry_in(carry_in),.sum(sum[0]),.carry_out(carry_out0));
myadder adder1(.a(a[1]),.b(b[1]),.c(c[1]),.d(d[1]),.carry_in(carry_out0),.sum(sum[1]),.carry_out(carry_out1));
myadder adder2(.a(a[2]),.b(b[2]),.c(c[2]),.d(d[2]),.carry_in(carry_out1),.sum(sum[2]),.carry_out(carry_out2));
myadder adder3(.a(a[3]),.b(b[3]),.c(c[3]),.d(d[3]),.carry_in(carry_out2),.sum(sum[3]),.carry_out(carry_out3));
myadder adder4(.a(a[4]),.b(b[4]),.c(c[4]),.d(d[4]),.carry_in(carry_out3),.sum(sum[4]),.carry_out(carry_out4));
myadder adder5(.a(a[5]),.b(b[5]),.c(c[5]),.d(d[5]),.carry_in(carry_out4),.sum(sum[5]),.carry_out(carry_out5));
myadder adder6(.a(a[6]),.b(b[6]),.c(c[6]),.d(d[6]),.carry_in(carry_out5),.sum(sum[6]),.carry_out(carry_out6));
myadder adder7(.a(a[7]),.b(b[7]),.c(c[7]),.d(d[7]),.carry_in(carry_out6),.sum(sum[7]),.carry_out(carry_out7));
myadder adder8(.a(a[8]),.b(b[8]),.c(c[8]),.d(d[8]),.carry_in(carry_out7),.sum(sum[8]),.carry_out(carry_out8));
myadder adder9(.a(a[9]),.b(b[9]),.c(c[9]),.d(d[9]),.carry_in(carry_out8),.sum(sum[9]),.carry_out(carry_out9));
myadder adder10(.a(a[10]),.b(b[10]),.c(c[10]),.d(d[10]),.carry_in(carry_out9),.sum(sum[10]),.carry_out(carry_out10));
myadder adder11(.a(a[11]),.b(b[11]),.c(c[11]),.d(d[11]),.carry_in(carry_out10),.sum(sum[11]),.carry_out(carry_out11));
myadder adder12(.a(a[12]),.b(b[12]),.c(c[12]),.d(d[12]),.carry_in(carry_out11),.sum(sum[12]),.carry_out(carry_out12));
myadder adder13(.a(a[13]),.b(b[13]),.c(c[13]),.d(d[13]),.carry_in(carry_out12),.sum(sum[13]),.carry_out(carry_out13));
myadder adder14(.a(a[14]),.b(b[14]),.c(c[14]),.d(d[14]),.carry_in(carry_out13),.sum(sum[14]),.carry_out(carry_out14));
myadder adder15(.a(a[15]),.b(b[15]),.c(c[15]),.d(d[15]),.carry_in(carry_out14),.sum(sum[15]),.carry_out(carry_out));
endmodule