加法器：generate语句的应用.txt

VHDL实例

-- n-bit Adder using the Generate Statement
-- download from: www.fpga.com.cn & www.pld.com.cn

library IEEE;
use IEEE.Std_logic_1164.all;

ENTITY addn IS
   GENERIC(n : POSITIVE := 3);   --no. of bits less one
   PORT(addend, augend : IN BIT_VECTOR(0 TO n);
         carry_in : IN BIT; carry_out, overflow : OUT BIT;
         sum : OUT BIT_VECTOR(0 TO n));
END addn;

ARCHITECTURE generated OF addn IS
   SIGNAL carries : BIT_VECTOR(0 TO n);
BEGIN
addgen : FOR i IN addend'RANGE 
   GENERATE
      lsadder : IF i = 0 GENERATE
         sum(i) <= addend(i) XOR augend(i) XOR carry_in;
         carries(i) <= (addend(i) AND augend(i)) OR
                       (addend(i) AND carry_in) OR
                       (carry_in AND augend(i));
         END GENERATE;
      otheradder : IF i /= 0 GENERATE
         sum(i) <= addend(i) XOR augend(i) XOR carries(i-1);
         carries(i) <= (addend(i) AND augend(i)) OR
                        (addend(i) AND carries(i-1)) OR
                        (carries(i-1) AND augend(i));
         END GENERATE;
   END GENERATE;
   carry_out <= carries(n);
   overflow <= carries(n-1) XOR carries(n);
END generated;