代码搜索：CPLD FPGA

找到约 10,000 项符合「CPLD FPGA」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/173063/9676057

qmsg pulse_count.fit.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
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www.eeworm.com/read/173063/9676079

qmsg pulse_count.tan.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
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www.eeworm.com/read/413398/11157640

c cpb40drvapi.c

/*============================================================= * Copyright (c) 2008~2010, CPIT. All Rights Reserved. * * MODULE: i2c 驱动 * * FILENAME: i2cDrv8548.c * * DESCRIPTION:i2c 驱动程序代码
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www.eeworm.com/read/300257/13923926

c c6711_ipb.c

/***************************************************************************** * File name : C6711_IPB.c * Description: *************************************************************************
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www.eeworm.com/read/300257/13924005

c c6711_dsk.c

/***************************************************************************** * File name : C6711_DSK.c * Description: *************************************************************************
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www.eeworm.com/read/235221/14081055

bak fpgadram.bak

#include #include unsigned int xdata start_addr; unsigned int xdata end_addr; unsigned int xdata address; unsigned int xdata data_address=0xa080; //双口RAM数据存放地址计数器 unsig
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www.eeworm.com/read/201251/15411985

cmd_log ddr_cntl_a.cmd_log

xst -ise "E:/hardware/KDVM26402/fpga/ddr_cntl_a_withtb/ddr_cntl_a_withtb" -intstyle ise -ifn ddr_cntl_a.xst -ofn ddr_cntl_a.syr ngdbuild -ise "E:/hardware/KDVM26402/fpga/ddr_cntl_a_withtb/ddr_cntl_a_
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www.eeworm.com/read/201251/15412028

v ddr_cntl_a_ddr1_test_bench_0.v

////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2005 Xilinx, Inc. // This design is confidential and proprietary of Xilinx, All Rights Reserved. ///////
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www.eeworm.com/read/201251/15412134

v ddr_cntl_a_ddr1_test_bench_0.v

////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2005 Xilinx, Inc. // This design is confidential and proprietary of Xilinx, All Rights Reserved. ///////
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www.eeworm.com/read/199511/7847032

asm 7279t_sdt.asm

;1、7279的INT 通过CPLD 接DSP的 FSX ;2、7279的CS 通过CPLD 接DSP的 FSR ;3、7279的CLK 通过CPLD 接DSP的 CLKX ;4、7279的DATA通过CPLD 接DSP的 CLKR ;************************************************************************** ;
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