ddr_cntl_a_ddr1_test_bench_0.v

arm控制FPGA的DDR测试代码

//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_ddr1_test_bench_0.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: This module comprises the command, address and data associated
//              with a write and a read command.
///////////////////////////////////////////////////////////////////////////////

`include "../rtl/ddr_cntl_a_parameters_0.v"

`timescale 1ns/100ps

module    ddr_cntl_a_ddr1_test_bench_0(    
                       fpga_clk,
	               fpga_rst90,
	               fpga_rst0,
	               fpga_rst180,
	               clk90,
 	               burst_done,
	               INIT_DONE,
                     auto_ref_req,
	               ar_done,
	               u_ack,
	               u_data_val,
	               u_data_o,
	               u_addr,
	               u_cmd,
	               u_data_i,
			u_data_m,
	               u_config_parms,
	               led_error_output,
		       data_valid_out
	               	               
                       );
                       
   input          fpga_clk;
   input          fpga_rst90;
   input          fpga_rst0;   
   input 	  	  fpga_rst180;
   input 	        clk90; 
   input 	        INIT_DONE;
   input          ar_done;
   input 	        u_ack;
   input          u_data_val;      
   input [(2*`data_width)-1:0]  u_data_o; 
   input           auto_ref_req;           
   
   output 	       burst_done;
   output [((`row_address + `col_ap_width + `bank_address)-1):0]  u_addr;
   output [2:0]   u_cmd;  
   output [(2*`data_width)-1:0] u_data_i;
   output [((`data_mask_width*2)-1):0] u_data_m;
   output [9:0]   u_config_parms;
   output         led_error_output;
   output         data_valid_out;
 
   
   wire           clk;
   wire           addr_inc;
   wire           addr_rst;
   wire           cmd_ack;
   wire           cnt_roll;
   wire           ctrl_ready;
   wire           data_valid;
   reg           lfsr_rst_r;
   wire           lfsr_rst_w;
   wire           r_w;
   wire [(2*`data_width)-1:0]   lfsr_data_w;
   wire [(2*`data_width)-1:0]   lfsr_data_r;   
   wire [((`data_mask_width*2)-1):0]  lfsr_data_m_r;
   wire [((`data_mask_width*2)-1):0]  lfsr_data_m_w;
   wire [((`row_address + `col_ap_width   + `bank_address)-1):0]  addr_out;
   wire [6:0]     state;
   reg            rst0_r;
   reg            rst90_r;
   reg            rst180_r;   
   reg            lfsr_ena_r;
   reg            lfsr_ena_w;
   reg	       u_dat_flag;
   wire	       u_dat_fl;

   wire lfsr_rst_r1;



//  Input : CONFIG REGISTER FORMAT 
// config_register = {   EMR(Enable/Disable DLL),
//                       BMR (Normal operation/Normal Operation with Reset DLL),
//                       BMR/EMR,
//                       CAS_latency (3),
//                       Burst type ,
//                       Burst_length (3) }
//
// Input : COMMAND REGISTER FORMAT
//          000  - NOP
//          001  - Precharge 
//          010  - Auto Refresh
//          011  - SElf REfresh
//          100  - Write Request
//          101  - Load Mode Register
//          110  - Read request
//          111  - Burst terminate
//
// Input : Address format
//   row address = input address(19 downto 8)
//   column addrs = input address( 7 downto 0)
//
// provide u_cmd
// provide u_config_parms
//
//  Terminals assignment 
//  Input terminals

assign clk         = fpga_clk;
assign cmd_ack     = u_ack;
assign data_valid  = u_data_val;

assign ctrl_ready  = 1'b1;

  assign u_addr[((`row_address + `col_ap_width   + `bank_address)-1):0] = addr_out[((`row_address + `col_ap_width   + `bank_address)-1):0];

assign u_data_i     = lfsr_data_w;
assign u_data_m     = lfsr_data_m_w;
assign u_config_parms = {3'b000 , `cas_latency_value ,1'b0, `burst_length} ;

always @ (posedge clk)
begin
  rst0_r <= fpga_rst0;
end

always @ (posedge clk90)
begin
  rst90_r <= fpga_rst90;
end

always @ (negedge clk)
begin
  rst180_r <= fpga_rst180;
end

always @ (posedge clk90)   // read lfsr_ena
begin
  if (rst90_r == 1'b1)
     lfsr_ena_r <= 1'b0;
  else if (u_data_val == 1'b1) 
     lfsr_ena_r <= 1'b1;
  else
     lfsr_ena_r <= 1'b0;
end

always @ (posedge clk90)    // write lfsr_ena
begin
  if (rst90_r == 1'b1)
     lfsr_ena_w <= 1'b0;
  else if ((r_w == 1'b0) && (u_ack == 1'b1))
     lfsr_ena_w <= 1'b1;
  else
     lfsr_ena_w <= 1'b0;
end

always@(posedge clk90)
begin
 if(rst90_r == 1'b1)
	u_dat_flag <= 1'b0;
 else
	u_dat_flag  <= cmd_ack;
end

assign u_dat_fl = cmd_ack && !u_dat_flag && r_w ;

assign lfsr_rst_r1 = u_dat_fl ;

always@(posedge clk90)
begin
 if(rst90_r == 1'b1)
	 lfsr_rst_r <= 1'b0;
 else
	 lfsr_rst_r <= lfsr_rst_r1;
 end 


ddr_cntl_a_addr_gen_0 INST1  ( 
                 .clk(~clk),
                  .rst(rst180_r),
                  .addr_rst(addr_rst),
                  .addr_inc(addr_inc),
                  .addr_out(addr_out),
                  .test_cnt_ena(ctrl_ready),
                  .burst_done(burst_done),
                  .cnt_roll(cnt_roll)
                  );
                  
ddr_cntl_a_cmd_fsm_0   INST_2  ( 
                  .clk(clk),
                  .clk90(clk90),
	           .cmd_ack(cmd_ack),
                  .cnt_roll(cnt_roll),
                  .r_w(r_w),
                  .refresh_done(ar_done),
                  .rst(rst0_r),
                  .rst90(rst90_r),
                  .rst180(rst180_r),
                  .init_val(INIT_DONE),
                  .u_data_val(u_data_val),
                  .addr_inc(addr_inc),
                  .addr_rst(addr_rst),
                  .u_cmd(u_cmd),
                  .init_counter(state),
                  .lfsr_rst(lfsr_rst_w)
                  );

ddr_cntl_a_cmp_data_0	INST3	( 
                  .clk(clk90),
                  .data_valid(data_valid),
                  .lfsr_data(lfsr_data_r),
                  .read_data(u_data_o),
                  .rst(rst90_r),
                  .led_error_output(led_error_output),
		  .data_valid_out(data_valid_out)
                                    );

ddr_cntl_a_lfsr32_0	INST5	( 
                .clk(clk90),
                .rst(rst90_r),
                .lfsr_rst(lfsr_rst_r),
                .lfsr_ena(lfsr_ena_r),
                .lfsr_data_m(lfsr_data_m_r),
                .lfsr_out(lfsr_data_r)
                );
                
ddr_cntl_a_lfsr32_0	INST7	( 
                .clk(clk90),
                .rst(rst90_r),
                .lfsr_rst(lfsr_rst_w),
                .lfsr_ena(lfsr_ena_w),
                .lfsr_data_m(lfsr_data_m_w),
                .lfsr_out(lfsr_data_w)
                );
                

endmodule