pulse_count.fit.qmsg

本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Web Edition " "Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 13 16:19:29 2006 " "Info: Processing started: Tue Jun 13 16:19:29 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off pulse_count -c pulse_count " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off pulse_count -c pulse_count" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "pulse_count EP2C5Q208C8 " "Info: Selected device EP2C5Q208C8 for design \"pulse_count\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208C8 " "Info: Device EP2C8Q208C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "19 19 " "Info: No exact pin location assignment(s) for 19 pins of 19 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[0\] " "Info: Pin PULSE_COUNT\[0\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[0] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[1\] " "Info: Pin PULSE_COUNT\[1\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[1\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[1] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[2\] " "Info: Pin PULSE_COUNT\[2\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[2\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[2] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[3\] " "Info: Pin PULSE_COUNT\[3\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[3\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[3] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[4\] " "Info: Pin PULSE_COUNT\[4\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[4\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[4] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[5\] " "Info: Pin PULSE_COUNT\[5\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[5\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[5] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[6\] " "Info: Pin PULSE_COUNT\[6\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[6\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[6] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[7\] " "Info: Pin PULSE_COUNT\[7\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[7\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[7] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[8\] " "Info: Pin PULSE_COUNT\[8\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[8\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[8] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[9\] " "Info: Pin PULSE_COUNT\[9\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[9\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[9] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[10\] " "Info: Pin PULSE_COUNT\[10\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[10\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[10] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[11\] " "Info: Pin PULSE_COUNT\[11\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[11\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[11] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[12\] " "Info: Pin PULSE_COUNT\[12\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[12\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[12] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[13\] " "Info: Pin PULSE_COUNT\[13\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[13\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[13] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[14\] " "Info: Pin PULSE_COUNT\[14\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[14\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[14] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "PULSE_COUNT\[15\] " "Info: Pin PULSE_COUNT\[15\] not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PULSE_COUNT\[15\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[15] } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { PULSE_COUNT[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "F4_CLK " "Info: Pin F4_CLK not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "F4_CLK" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { F4_CLK } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { F4_CLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "RESET " "Info: Pin RESET not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RESET" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { RESET } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { RESET } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DIRECTION " "Info: Pin DIRECTION not assigned to an exact location on the device" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DIRECTION" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { DIRECTION } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { DIRECTION } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "F4_CLK (placed in PIN 23 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node F4_CLK (placed in PIN 23 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "F4_CLK" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { F4_CLK } "NODE_NAME" } "" } } { "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" { Floorplan "D:/altera/fpga+dsp/pusle_count/pulse_count.fld" "" "" { F4_CLK } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}