代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
代码结果 10,000
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qmsg pwm_led.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
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txt 实验板连线说明.txt
异步通信:
电源模块中需要跳线.第一个跳线处左跳5V
只需将750K时钟信号与FPGA中的79脚GCLK1连接.
www.eeworm.com/read/366067/9833590
xrf clk_div5_modelsim.xrf
vendor_name = ModelSim
source_file = 1, D:/fpga例子/clk_div5/clk_div5.vhd
source_file = 1, D:/fpga例子/clk_div5/clk_div5.vwf
design_name = clk_div5
instance = comp, \clk~I\, clk, clk_div5, 1
instance
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qmsg clk_div5.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
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qmsg led.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Runni
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ref hdpdeps.ref
V3 12
FL E:/FPGA/Exp4-Clock/SEG.vhd 2006/06/23.14:39:16 I.24
EN work/SEG 1151044791 FL E:/FPGA/Exp4-Clock/SEG.vhd PB ieee/std_logic_1164 1131108373 \
PB ieee/std_logic_arith 11311
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ucf top.ucf
#####################
# clock constraints #
#####################
#
#specifying clock periods
#133 MHz
NET "sys_clk" PERIOD = 7.5ns ;
NET "fpga_clk" PERIOD = 7.5ns ;
NET "fpga_clk2x" PERIOD
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prj uart_test_syn.prj
#add_file options
add_file -verilog "E:/所有其他/安装文件/FPGA/actel/实验例程/UART/hdl/rec.v"
add_file -verilog "E:/所有其他/安装文件/FPGA/actel/实验例程/UART/hdl/send.v"
add_file -verilog "E:/所有其他/安装文件/FPGA/actel/实验例程/UA
www.eeworm.com/read/161070/10456685
rsp _editucf.rsp
D:/XILINX_WEBPACK/BIN/NT
key2
_editucf.err
d:/xilinx_webpack/data/ucf.tft
key2.ucf
fpga
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ref hdllib.ref
PH pck_s2v NULL F:/FPGA_LMS4/FPGA_LMS3/PCK_S2V.vhd sub00/vhpl02
PB pck_s2v pck_s2v F:/FPGA_LMS4/FPGA_LMS3/PCK_S2V.vhd sub00/vhpl03
EN lms NULL F:/FPGA_LMS4/FPGA_LMS3/LMS.vhd sub00/vhpl00
AR lms beh