hdpdeps.ref

数字计时器

V3 12
FL E:/FPGA/Exp4-Clock/SEG.vhd 2006/06/23.14:39:16 I.24
EN work/SEG 1151044791             FL E:/FPGA/Exp4-Clock/SEG.vhd PB ieee/std_logic_1164 1131108373 \
      PB ieee/std_logic_arith 1131108375 PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/SEG/BEHAVIORAL 1151044792  FL E:/FPGA/Exp4-Clock/SEG.vhd EN work/SEG 1151044791 \
      CP COUNT10        CP COUNT6
EN work/COUNT10 1151044793         FL E:/FPGA/Exp4-Clock/SEG.vhd PB ieee/std_logic_1164 1131108373 \
      PB ieee/std_logic_arith 1131108375 PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/COUNT10/BEHAVIORAL 1151044794 FL E:/FPGA/Exp4-Clock/SEG.vhd EN work/COUNT10 1151044793
EN work/COUNT6 1151044795          FL E:/FPGA/Exp4-Clock/SEG.vhd PB ieee/std_logic_1164 1131108373 \
      PB ieee/std_logic_arith 1131108375 PB ieee/STD_LOGIC_UNSIGNED 1131108379
AR work/COUNT6/BEHAVIORAL 1151044796 FL E:/FPGA/Exp4-Clock/SEG.vhd EN work/COUNT6 1151044795
FL g:/doc/file/seg/SEG.vhd 2002/06/30.09:03:48 I.24
FL G:/doc/file/seg/SEG.vhd 2002/07/03.14:53:10 I.24
FL G:/doc/seg100/SEG.vhd 2002/08/19.10:29:22 I.24