代码搜索：CMOS芯片
找到约 8,079 项符合「CMOS芯片」的源代码
代码结果 8,079
www.eeworm.com/read/270618/11031762
txt cmos密码清除方法.txt
打开机箱，找到主板上的电池，将其与主板的连接断开（就是取下电池喽），此时CMOS将因断电而失去内部储存的一切信息。再将电池接通，合上机箱开机，由于CMOS已是一片空白，它将不再要求你输入密码，此时进入BIOS设置程序，选择主菜单中的"LOAD BIOS DEFAULT"（装入BIOS缺省值）或"LOAD SETUP DEFAULT"（装入设置程序缺省值）即可，前者以最安全的方式启动计算机，后者能使 ...
www.eeworm.com/read/328490/13024440
txt cmos密码清除方法.txt
打开机箱，找到主板上的电池，将其与主板的连接断开（就是取下电池喽），此时CMOS将因断电而失去内部储存的一切信息。再将电池接通，合上机箱开机，由于CMOS已是一片空白，它将不再要求你输入密码，此时进入BIOS设置程序，选择主菜单中的"LOAD BIOS DEFAULT"（装入BIOS缺省值）或"LOAD SETUP DEFAULT"（装入设置程序缺省值）即可，前者以最安全的方式启动计算机，后者能使 ...
www.eeworm.com/read/315669/13538547
prj cmos_fifo_usb.prj
KEY LIBERO "8.0"
KEY CAPTURE "8.0.0.40"
KEY DEFAULT_IMPORT_LOC "F:\FPGA_TOP0415\hdl"
KEY DEFAULT_OPEN_LOC "C:\Documents and Settings\Administrator\桌面"
KEY HDLTechnology "VERILOG"
KEY VendorTechno
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v cmos_fifo_tb.v
// cmos_fifo_tb.v
`timescale 1ns/100ps
module cmos_fifo_tb ( tb_rd );
reg tb_wclk;
reg tb_reset;
reg tb_rst;
reg
www.eeworm.com/read/315669/13538551
plg cmos_fifo_usb.plg
@P: Worst Slack : 2.091
@P: cmos_fifo_usb|wclk - Estimated Frequency : 126.4 MHz
@P: cmos_fifo_usb|wclk - Requested Frequency : 100.0 MHz
@P: cmos_fifo_usb|wclk - Estimated Period : 7.909
@P:
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msg cmos_fifo_usb.msg
@TM:1211332026
@N: BN225 :"":0:0:0:-1|Writing default property annotation file H:\fpga_test\cmos_fifo_usb\synthesis\cmos_fifo_usb.map.
@N: MF249 :"":0:0:0:-1|Running in 32-bit mode.
@N: MT195 :"":0
www.eeworm.com/read/315669/13538554
srd cmos_fifo_usb.srd
f "noname"; #file 0
f "c:\libero\synplify\synplify_88a1\lib\proasic\proasic3.v"; #file 1
f "h:\fpga_test\cmos_fifo_usb\smartgen\two_port1280x8\two_port1280x8.v"; #file 2
f "h:\fpga_test\cmos_fifo_u
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areasrr cmos_fifo_usb.areasrr
----------------------------------------------------------------------
Report for cell cmos_fifo_usb.verilog
Cell usage:
cel
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srr cmos_fifo_usb.srr
#Build: Synplify 8.8A1, Build 015R, Apr 16 2007
#install: C:\Libero\Synplify\Synplify_88A1
#OS: Windows XP 5.1
#Hostname: ZHOUHUAGOU
#Implementation: synthesis
#Wed May 21 14:37:58 2008
$
www.eeworm.com/read/315669/13538557
srs cmos_fifo_usb.srs
@E
@
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.7.5, Build 159R from Synplicity, Inc.
# Copyright 1994-2007 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written