cmos_fifo_usb.msg

cmos数据到fifo再到usb的fifo部分程序(68013a)

@TM:1211332026
@N: BN225 :"":0:0:0:-1|Writing default property annotation file H:\fpga_test\cmos_fifo_usb\synthesis\cmos_fifo_usb.map.
@N: MF249 :"":0:0:0:-1|Running in 32-bit mode.
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":854:7:854:10|Synthesizing module DFN1
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1094:7:1094:9|Synthesizing module GND
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1238:7:1238:9|Synthesizing module MX2
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1377:7:1377:9|Synthesizing module OR2
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1383:7:1383:10|Synthesizing module OR2A
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1705:7:1705:9|Synthesizing module VCC
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1927:8:1927:16|Synthesizing module RAM512X18
@N: CG364 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":8:12:8:24|Synthesizing module cmos_fifo_usb
@W: CL159 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":23:20:23:22|M
@W: CL159 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":28:20:28:24|M
@TM:1211351086
@W: CG133 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":63:20:63:29|M
@W: CG133 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":72:20:72:26|M
@W: CL156 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":122:20:122:21|M
@W: CL168 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":134:19:134:20|M
@N:  :"h:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":167:4:167:9|M
@N:  :"h:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":215:4:215:9|M
@N:  :"h:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":227:6:227:11|M
@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":251:4:251:9|M
@W: CL154 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":276:4:276:9|M
@W: CL156 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":276:4:276:9|M
@W: CL171 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":276:4:276:9|M
@W: CL189 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":276:4:276:9|M
@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":288:4:288:9|M
@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":300:4:300:9|M
@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":312:4:312:9|M
@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":324:4:324:9|M
@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":339:4:339:9|M
@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":351:4:351:9|M
@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":363:4:363:9|M
@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":374:4:374:9|M
@TM:1211332026
@N: CG364 :"H:\fpga_test\cmos_fifo_usb\smartgen\two_port1280x8\two_port1280x8.v":5:7:5:20|Synthesizing module two_port1280x8
@W: CL168 :"H:\fpga_test\cmos_fifo_usb\smartgen\two_port1280x8\two_port1280x8.v":162:9:162:19|M
@W: CL168 :"H:\fpga_test\cmos_fifo_usb\smartgen\two_port1280x8\two_port1280x8.v":197:9:197:19|M
@N: CG364 :"H:\fpga_test\cmos_fifo_usb\smartgen\usb_fifo32x16\usb_fifo32x16.v":5:7:5:19|Synthesizing module usb_fifo32x16