代码搜索：CASE
找到约 10,000 项符合「CASE」的源代码
代码结果 10,000
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v sevenseg_case.v
module sevenseg_case(up_down,seg,clk);
input clk;
input up_down;
output[7:0]seg;
reg[7:0]seg;
reg [3:0]hex;
reg[24:0]counter;
reg clk_div;
reg udreg;
always@(posedge clk)
begin
if (cou
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qws sevenseg_case.qws
[ProjectWorkspace]
ptn_Child1=Frames
ptn_Child2=ActionPoints
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
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ppl sevenseg_case.ppl
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hif sevenseg_case.hif
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
5
352
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
sevenseg_case
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
#
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psp sevenseg_case.psp
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qsf sevenseg_case.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
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vhd case1.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY case1 IS
PORT ( table_in1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
table_out1 : OUT INTEGER RANG
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vhd case0.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY case0 IS
PORT ( table_in0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
table_out0 : OUT INTEGER RANG
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vhd case2.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY case2 IS
PORT ( table_in2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
table_out2 : OUT INTEGER RANG