sevenseg_case.v

来自「sevenseg_case verilog code」· Verilog 代码 · 共 58 行

module sevenseg_case(up_down,seg,clk);
input clk;
input up_down;
output[7:0]seg;

reg[7:0]seg;
reg [3:0]hex;
reg[24:0]counter;
reg clk_div;
reg udreg;

always@(posedge clk)
begin 
if (counter<33330000)
begin
clk_div=0;
counter=counter+1;
end
else
begin
	clk_div=1;
	counter=0;
end 
end

always@(posedge clk_div) 
begin
case(hex)
4'd0:seg=8'b11000000;
4'd1:seg=8'b11111001;
4'd2:seg=8'b10100100;
4'd3:seg=8'b10110000;
4'd4:seg=8'b10011001;
4'd5:seg=8'b10010010;
4'd6:seg=8'b10000010;
4'd7:seg=8'b11111000;
4'd8:seg=8'b10000000;
4'd9:seg=8'b10010000;
4'd10:seg=8'b10001000;
4'd11:seg=8'b10000011;
4'd12:seg=8'b11000110;
4'd13:seg=8'b10100001;
4'd14:seg=8'b10000110;
4'd15:seg=8'b10001110;
default:seg=8'b11000000;
endcase

if(udreg
)
hex=hex+1;
else
hex=hex-1;
end 

always@(posedge up_down)
udreg=~udreg;

endmodule