case2.vhd

来自「vhdl代码 实现16阶fir滤波器」· VHDL 代码 · 共 41 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY case2 IS
       PORT ( table_in2  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
              table_out2 : OUT INTEGER RANGE 0 TO 8283);
END case2;

ARCHITECTURE LCs OF case2 IS
BEGIN

-- This is the DA CASE table for
-- the 4 coefficients: 2591, 2357, 1934, 1401  
-- automatically generated with dagen.exe -- DO NOT EDIT!

  PROCESS (table_in2)
  BEGIN
    CASE table_in2 IS 
      WHEN  "0000" =>    table_out2 <=  0;
      WHEN  "0001" =>    table_out2 <=  2591;
      WHEN  "0010" =>    table_out2 <=  2357;
      WHEN  "0011" =>    table_out2 <=  4948;
      WHEN  "0100" =>    table_out2 <=  1934;
      WHEN  "0101" =>    table_out2 <=  4525;
      WHEN  "0110" =>    table_out2 <=  4291;
      WHEN  "0111" =>    table_out2 <=  6882;
      WHEN  "1000" =>    table_out2 <=  1401;
      WHEN  "1001" =>    table_out2 <=  3992;
      WHEN  "1010" =>    table_out2 <=  3758;
      WHEN  "1011" =>    table_out2 <=  6349;
      WHEN  "1100" =>    table_out2 <=  3335;
      WHEN  "1101" =>    table_out2 <=  5926;
      WHEN  "1110" =>    table_out2 <=  5692;
      WHEN  "1111" =>    table_out2 <=  8283;
      WHEN   OTHERS  =>    table_out2 <=  0;
    END CASE;
  END PROCESS;

END LCs;