代码搜索：Bit
找到约 10,000 项符合「Bit」的源代码
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www.eeworm.com/read/487590/6506053
vhd t102.vhd
--
-- This file tests Support for user defined procedures.
--
entity TEST is
port( A : in bit_vector(0 to 3);
Z : out bit);
end TEST;
architecture T102 of TEST is
procedure parity
www.eeworm.com/read/478303/6714490
vhd ex_p5_27_look_ahead_adder.vhd
entity LA_CARRY is
port (A,B: in BIT_VECTOR(3 downto 0);Cin:in BIT;
C:out BIT_VECTOR(1 to 4));
end LA_CARRY;
architecture DF of LA_CARRY is
signal G0,G1,G2,G3,C1,C2,C3,P0,P1,P2,P3: BIT;
begin
www.eeworm.com/read/477052/6744634
c bitarray.c
/* +++Date last modified: 05-Jul-1997 */
/*
** Functions to maintain an arbitrary length array of bits
*/
#include "bitops.h"
char *alloc_bit_array(size_t bits)
{
char *set = calloc((bits +
www.eeworm.com/read/347629/11652876
vhd 40_generic_dec.vhd
package logic is
type Bit_vector is array (Natural range ) of Bit;
end logic;
use WORK.logic.all;
entity And2 is
port( I1,I2: Bit; O1: out Bit);
end and2;
architecture And2_archit of
www.eeworm.com/read/347629/11652997
vhd 40_generic_dec.vhd
package logic is
type Bit_vector is array (Natural range ) of Bit;
end logic;
use WORK.logic.all;
entity And2 is
port( I1,I2: Bit; O1: out Bit);
end and2;
architecture And2_archit of
www.eeworm.com/read/347629/11653059
vhd 59_decoder.vhd
entity decoder is
port( I0 : in Bit;
I1 : in Bit;
O0 : out Bit;
O1 : out Bit;
O2 : out Bit;
O3 : out Bit);
end entity;
architecture decoder_archi of decoder is
signal
www.eeworm.com/read/156687/11785088
h io_map.h
/** ###################################################################
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
** Filename : IO_Map.H
** Project : _2006_01_0
www.eeworm.com/read/155849/11843849
asm sio.asm
*
* "Bit-bang" serial I/O functions for the 8051.
*
* These routines transmit and receive serial data using two general
* I/O pins, in 8 bit, No parity, 1 stop bit format. They are useful
* for p
www.eeworm.com/read/344008/11913152
h compiler.h
#ifndef __COMPILER_H__
#define __COMPILER_H__
#ifdef __IMAGECRAFT__
// choose your AVR device here
#include
#include
#define outp(val, reg) (reg = val)
#define
www.eeworm.com/read/153614/12020953
vhd 40_generic_dec.vhd
package logic is
type Bit_vector is array (Natural range ) of Bit;
end logic;
use WORK.logic.all;
entity And2 is
port( I1,I2: Bit; O1: out Bit);
end and2;
architecture And2_archit of