代码搜索:Bit

找到约 10,000 项符合「Bit」的源代码

代码结果 10,000
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vhd 40_generic_dec.vhd

package logic is type Bit_vector is array (Natural range ) of Bit; end logic; use WORK.logic.all; entity And2 is port( I1,I2: Bit; O1: out Bit); end and2; architecture And2_archit of
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c camproset.c

/****************************************************************************** Filename: camproset.c Descriptions - Camera Processor Initialization code using IIC. History - July 23, 2003.
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c hnr_s5.c

//DS18B20温度测量实验 //在 “1602字符型液晶显示实验” 的基础上修改 //功能:在数码管上显示当前DS18B20测到的温度 //小数部分为4位,温度为负时,最高位显示"-" //测量范围:-55℃ ~ +125℃ /* 将多功能模块电路板接到P3口, 需要将电路板16*2液晶模块接到J12的LCD接口上,注意引脚顺序。 */ #include "msp
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vhd vhdl code1.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ffT IS PORT(T,CLK1,RESET:IN BIT; Q,QINV:OUT BIT); END ffT; ARCHITECTURE behav OF ffT IS SIGNAL S:BIT; BEGIN PROCESS BEGIN WAIT UNTIL CLK1='
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vhd vhdl code1.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;//standard library packages ENTITY fullsubs IS PORT(A,B,BORIN: IN BIT; DIFF,BOR:OUT BIT); );//input and output declaration END fullsubs; ARCHITECTURE st
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bak vhdl code1.bak

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;//standard library packages ENTITY fullsubs IS PORT(A,B,BORIN: IN BIT; DIFF,BOR:OUT BIT); );//input and output declaration END fullsubs; ARCHITECTURE st
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m sphit_main_decode.m

% Code started 31th Oct 2003, Ex taken from J.M.Shapiro's paper on EZW % This code is not intented to be optimized, just to make things work % and to understand the principles of SPHIT % Reference
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lst netlist.lst

G:\vijay_FPGA_LAB\4bit_alu\alu_4bit.ngc 1139901278 OK
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log map.log

Mapping Module alu_4bit . . . MAP command line: map -intstyle ise -p xc3s50-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o alu_4bit_map.ncd alu_4bit.ngd alu_4bit.pcf Mapping Module alu_4bit: DONE
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log par.log

Place & Route Module alu_4bit . . . PAR command line: par -w -intstyle ise -ol std -t 1 alu_4bit_map.ncd alu_4bit.ncd alu_4bit.pcf PAR completed successfully