代码搜索:Behavioural
找到约 91 项符合「Behavioural」的源代码
代码结果 91
www.eeworm.com/read/347114/11695463
dat behavioural.dat
www.eeworm.com/read/347114/11695464
psm behavioural.psm
www.eeworm.com/read/347114/11697928
dat behavioural.dat
www.eeworm.com/read/347114/11697930
psm behavioural.psm
www.eeworm.com/read/17605/740753
dat behavioural.dat
www.eeworm.com/read/17605/741565
dat behavioural.dat
www.eeworm.com/read/169726/9844917
txt behavioural model of a simple 8-bit cpu.txt
Behavioural model of a simple 8-bit CPU
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.bv_math.ALL;
USE work.cpu8pac.ALL;
ENTITY cpu IS
GENERIC(cycle_time : TIME := 200 ns); --must be
www.eeworm.com/read/428603/8856523
vhd debounce.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; -- use for da, comment out for actmap
use ieee.std_logic_arith.all;
entity debounce is
port(clk,button : in std_logic;
www.eeworm.com/read/433021/8551904
vhd 移位寄存器_8bit.vhd
--Behavioural description of an 8-bit Shift Register
--8-bit universal shift register modelled using a process
ENTITY shftreg8 IS
PORT(clock, serinl, serinr : IN BIT; --clock and serial inputs
mode :
www.eeworm.com/read/366115/9832412
vhd clockdiv.vhd
library ieee;
use ieee.std_logic_1164.all;
entity clockdiv is
port(
clockin : in std_logic;
clockout : out std_logic );
end clockdiv;
architecture behavioural of clockdiv is