移位寄存器_8bit.vhd

含有各类寄存器

--Behavioural description of an 8-bit Shift Register
--8-bit universal shift register modelled using a process
ENTITY shftreg8 IS
PORT(clock, serinl, serinr : IN BIT; --clock and serial inputs
mode : IN BIT_VECTOR(0 TO 1);
--"00" : disabled; "10" : shift left; "01" : shift right; "11" : Parallel
load;
parin : IN BIT_VECTOR(0 TO 7); --parallel inputs
parout : OUT BIT_VECTOR(0 TO 7)); --parallel outputs
END shftreg8;
ARCHITECTURE behavioural OF shftreg8 IS
BEGIN
PROCESS
--declare variable to hold register state
VARIABLE state : BIT_VECTOR(0 TO 7) := "00000000";
BEGIN
--synchronise process to rising edges of clock
WAIT UNTIL clock'EVENT AND clock = '1';
CASE mode IS
WHEN "00" => state := state; --disabled
WHEN "10" =>
FOR i IN 0 TO 7 LOOP --shift
left
IF i = 7 THEN
state(i) := serinl;
ELSE
state(i) := state(i + 1);
END IF;
END LOOP;
WHEN "01" =>
FOR i IN 7 DOWNTO 0 LOOP --shift
right
IF i = 0 THEN
state(i) := serinr;
ELSE
state(i) := state(i - 1);
END IF;
END LOOP;
WHEN "11" => state := parin; --parallel
load
END CASE;
--assign variable to parallel output port
parout <= state;
END PROCESS;
END behavioural;