代码搜索：ADPLL
找到约 28 项符合「ADPLL」的源代码
代码结果 28
www.eeworm.com/read/312900/13601945
v tb_adpll.v
`timescale 1ns/1ns
module tb_adpll;
reg clk;
reg reset;
reg signal_in;
wire signal_out;
wire syn;
wire dpout;
wire addclk;
wire delclk;
integer k;
integer f;
adpll dut(.n_reset(r
www.eeworm.com/read/173473/9655918
bak adpll.v.bak
module ADPLL(clk,clk_in,rst,limit,clk_out);
parameter cnt_size=9;
parameter del=1;
parameter duty=2;
parameter cycle_time=200;
input clk,clk_in,rst;
input [cnt_size-1:0]limit;
www.eeworm.com/read/173473/9655922
v tb_adpll.v
module tb_ADPLL();
parameter del=1;
parameter cnt_size=4;
parameter cycle_time=200;
reg clk,rst;
wire clk_in,clk_out;
integer counter;
reg[cnt_size-1:0]limit;
www.eeworm.com/read/245509/12796718
bak tb_adpll.v.bak
module tb_ADPLL();
parameter del=1;
parameter cnt_size=9;
parameter cycle_time=200;
reg clk,rst;
wire clk_in,clk_out;
integer counter;
reg[cnt_size-1:0]limit;
www.eeworm.com/read/173473/9655912
bak tb_adpll.v.bak
module tb_ADPLL();
parameter del=1;
parameter cnt_size=9;
parameter cycle_time=200;
reg clk,rst;
wire clk_in,clk_out;
integer counter;
reg[cnt_size-1:0]limit;
www.eeworm.com/read/374918/9379150
pdf a low jitter adpll for mobile applications.pdf
www.eeworm.com/read/245509/12796693
_info
m255
13
cModel Technology
dD:\WorkStation\ModelSim\666_design\pll
vADPLL
I;a?G5>I?mkGCH`WaYQ>_M3
VnNMd6V=9jO``Nn;gzc;Wz3
dE:\liang\testbench\45666035ADPLL\ADPLL
w1158810080
FE:/liang/testbench/4566603
www.eeworm.com/read/173473/9655900
_info
m255
13
cModel Technology
dD:\WorkStation\ModelSim\666_design\pll
vADPLL
IjB@W6_z0IYHEXecRbWj[;2
VnNMd6V=9jO``Nn;gzc;Wz3
dD:\WorkStation\ModelSim\666_design\ADPLL
w1158810080
FD:/WorkStation/ModelSim/
www.eeworm.com/read/334090/12640219
asm intvec.asm
;=====================================================================
; company: COMMIT Incorporated
; department: HW