tb_adpll.v

来自「全数字锁相环 功能与74297相同 提供参数配置」· Verilog 代码 · 共 41 行

`timescale 1ns/1ns
module tb_adpll;
	reg clk;
	reg reset;
    reg signal_in; 
	wire signal_out;
	wire syn;
	wire dpout;
	wire addclk;
	wire delclk;
    integer k;
   integer f;
   adpll dut(.n_reset(reset),.clk(clk),.signal_in(signal_in),.signal_out(signal_out),.syn(syn),.dpout(dpout),.delclk(delclk),.addclk(addclk));
	initial
	begin
	   clk <= 0;
	   reset<= 1;
	   signal_in<=0;
	end

	initial
    for(k=0;k<10000;k=k+1)  
    begin    //generate clk
		#5  clk <= 1'b0;
		#5  clk <= 1'b1;
	end   
	initial     
	begin       //generate reset
	    #5 reset<=0;
	    #5 reset<=1;
//   for(f=10;f<5000;f=f+10)
//		for(k=0;k<1000;k=k+1)   
//			   #f	signal_in<=~signal_in;
      #200 signal_in<=1; 
		for(k=0;k<10000;k=k+1)
		
		#320 signal_in<=~signal_in;
		$display( "All Test Complete." );
		$stop;
   end
endmodule