_info

verilog ADPLL file with testbench.v

m255
13
cModel Technology
dD:\WorkStation\ModelSim\666_design\pll
vADPLL
IjB@W6_z0IYHEXecRbWj[;2
VnNMd6V=9jO``Nn;gzc;Wz3
dD:\WorkStation\ModelSim\666_design\ADPLL
w1158810080
FD:/WorkStation/ModelSim/666_design/ADPLL/ADPLL.v
L0 1
VnNMd6V=9jO``Nn;gzc;Wz3
OE;L;6.1b;31
r1
31
o-work work
tGenerateLoopIterationMax 100000
n@a@d@p@l@l
vtb_ADPLL
I1g@FPz]1X8>_0`FP8Q`o00
VHdWX7P;[gLEbXR6JIb7_k1
dD:\WorkStation\ModelSim\666_design\ADPLL
w1158810078
FD:/WorkStation/ModelSim/666_design/ADPLL/tb_ADPLL.v
L0 1
VHdWX7P;[gLEbXR6JIb7_k1
OE;L;6.1b;31
r1
31
o-work work
tGenerateLoopIterationMax 100000
ntb_@a@d@p@l@l