代码搜索：ADPLL
找到约 28 项符合「ADPLL」的源代码
代码结果 28
www.eeworm.com/read/245509/12796725
v adpll.v
module ADPLL(clk,clk_in,rst,limit,clk_out);
parameter cnt_size=4;
parameter del=1;
parameter duty=2;
parameter cycle_time=200;
input clk,clk_in,rst;
input [cnt_size-1:0]limit;
www.eeworm.com/read/245509/12796744
mpf adpll.mpf
; Copyright Mentor Graphics Corporation 2004
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR IT
www.eeworm.com/read/312900/13601944
v adpll.v
/*
all digital phase lock loop
2008.2.27
v1.0
by lizhihzou
DPLL由 鉴相器 模K加减计数器 脉冲加减电路 同步建立侦察电路 模N分频器 构成.
整个系统的中心频率(即signal_in和signal_out的码速率的2倍
为clk/8/N. 模K加减计
www.eeworm.com/read/173473/9655914
v adpll.v
module ADPLL(clk,clk_in,rst,limit,clk_out);
parameter cnt_size=4;
parameter del=1;
parameter duty=2;
parameter cycle_time=200;
input clk,clk_in,rst;
input [cnt_size-1:0]limit;
www.eeworm.com/read/173473/9655916
mpf adpll.mpf
; Copyright Mentor Graphics Corporation 2005
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR IT
www.eeworm.com/read/245509/12796688
hif tb_adpll.hif
HIF003
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, an
www.eeworm.com/read/245509/12796722
acf tb_adpll.acf
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any
www.eeworm.com/read/245509/12796729
bak adpll.v.bak
module ADPLL(clk,clk_in,rst,limit,clk_out);
parameter cnt_size=9;
parameter del=1;
parameter duty=2;
parameter cycle_time=200;
input clk,clk_in,rst;
input [cnt_size-1:0]limit;
www.eeworm.com/read/245509/12796735
v tb_adpll.v
module tb_ADPLL();
parameter del=1;
parameter cnt_size=4;
parameter cycle_time=200;
reg clk,rst;
wire clk_in,clk_out;
integer counter;
reg[cnt_size-1:0]limit;