tb_adpll.v

一个自己编写的全数字锁相环及其测试向量

module tb_ADPLL();
    parameter del=1;
    parameter cnt_size=4;
    parameter cycle_time=200;
    
    reg clk,rst;
    wire clk_in,clk_out;
    
    integer counter;
    reg[cnt_size-1:0]limit;
    integer cycle_count;
    integer case_count;
    integer lock_count;
    
    reg reg_in;
    
    assign #del clk_in=(counter==0)? 1'b1:1'b0;
     ADPLL m1(clk,clk_in,rst,limit,clk_out);
     initial 
     begin
         clk=0;
         cycle_count=0;
         case_count=0;
             lock_count=0;
             counter=0;
             rst=1;
             limit=15;
             #120 rst=0;
     end
     always #(cycle_time/2) clk= ~clk;
     always@(posedge clk)
     begin
         if(lock_count === 3)
         begin
            $display("ADPLL has locked onto clock after %d cycles\n:",
                     cycle_count);
             case(case_count)
                 0:limit=10;
                 1:limit=5;
                 2:limit=7;
                 3:limit=6;
                 4:limit=12;
                 5:limit=10;
                 6:begin
                    $display("\nSimulation complete - errors\n");
                    $finish;
                   end
             endcase
             lock_count=0;
             counter <=#del 0;
             case_count=case_count +1;
             cycle_count=0;     
          end
          if(cycle_count >=16*16)
          begin
             $display("nERROR at time %0t:",$time);
             $display("  Clock is not locking\n");
             $stop;
          end
          begin
          if(counter === 0)
          begin
             counter<= #del limit;
          end
          else
          begin
             counter<=#del counter-1;
             cycle_count=cycle_count+1;
          end
          end
      end
      
      always@(negedge clk)
      begin
          if(!reg_in & clk_out)
           begin
               lock_count=lock_count+1;
           end
          else if(lock_count !==0)
           begin
               lock_count=0;
           end
           reg_in<=clk_out;
      end
  endmodule