adpll.v

一个自己编写的全数字锁相环及其测试向量

module ADPLL(clk,clk_in,rst,limit,clk_out);
    parameter cnt_size=4;
    parameter del=1;
    parameter duty=2;
    parameter cycle_time=200;
    input clk,clk_in,rst;
    input [cnt_size-1:0]limit;
    output clk_out;
    reg clk_out;
    
    time edge_time;
    time period;
    time clk_high;
    time high_time;
    // initialize regs
    initial 
    begin
        wait(period !==64'hxxxxxxxxxxxxxxxx);
        @(posedge clk);
        #del;
        clk_high =$time;
        high_time =$time;
    end
    // generate the output clock
    always@(clk_high)
    begin
        if(clk_high==high_time)
         begin
             edge_time=$time;
             clk_out<=1'b1;
             clk_out<= #(period -period/duty) 1'b0;
             high_time= $time +period;
             clk_high <= #period (high_time);
         end
    end
    
    always@(posedge clk_in)
    begin
        if(($time-edge_time !=0)&&($time-edge_time !=period))
         begin
              if(period-($time-edge_time)> cycle_time/2)
               begin
                   high_time=high_time - cycle_time;
                   clk_high <= #(high_time-$time) high_time;
               end
              else if(($time-edge_time)>= cycle_time/2)
               begin
                   high_time=high_time+cycle_time;
                   clk_high <=#(high_time-$time) high_time;
               end
         end
    end
    
    // look for changes in the target clock period
    always@(limit)
    begin
        @(posedge clk)
         period <=#del(limit+1)*cycle_time;
    end
endmodule