代码搜索：74ls256
找到约 12 项符合「74ls256」的源代码
代码结果 12
www.eeworm.com/read/21695/838822
prt chips.prt
FILE_TYPE=LIBRARY_PARTS;
primitive '74LS256';
pin
end_pin;
body
BODY_NAME='74LS256';
PHYS_DES_PREFIX='U';
CLASS='IC';
end_body;
end_primitive;
END.
www.eeworm.com/read/39074/1119658
prt chips.prt
FILE_TYPE=LIBRARY_PARTS;
primitive '74LS256';
pin
end_pin;
body
BODY_NAME='74LS256';
PHYS_DES_PREFIX='U';
CLASS='IC';
end_body;
end_primitive;
END.
www.eeworm.com/read/21695/838797
dat revision.dat
(Cell 74ls256
(RevisionInfoBlock
(Baselined 0)
(Revision 0.0.2)
(ModificationStatus NULL)
(Status Created)
(ErrorStatus 0)
(CreateInfo
(Time 04/30/09,10:31:19)
(User Admi
www.eeworm.com/read/21695/838825
dat revision.dat
(Cell 74ls256
(RevisionInfoBlock
(Baselined 0)
(Revision 0.0.1)
(ModificationStatus NULL)
(Status Created)
(ErrorStatus 0)
(CreateInfo
(Time 04/30/09,15:04:55)
(User Admi
www.eeworm.com/read/39074/1119633
dat revision.dat
(Cell 74ls256
(RevisionInfoBlock
(Baselined 0)
(Revision 0.0.2)
(ModificationStatus NULL)
(Status Created)
(ErrorStatus 0)
(CreateInfo
(Time 04/30/09,10:31:19)
(User Admi
www.eeworm.com/read/39074/1119661
dat revision.dat
(Cell 74ls256
(RevisionInfoBlock
(Baselined 0)
(Revision 0.0.1)
(ModificationStatus NULL)
(Status Created)
(ErrorStatus 0)
(CreateInfo
(Time 04/30/09,15:04:55)
(User Admi
www.eeworm.com/read/21695/838791
v verilog.v
// generated by newgenasym Thu Apr 30 11:30:12 2009
module \74ls256 (a, \clr* , cp, \e* , \es* , o, \ps* );
input [8:0] a;
input \clr* ;
input cp;
input \e* ;
input \es* ;
www.eeworm.com/read/39074/1119627
v verilog.v
// generated by newgenasym Thu Apr 30 11:30:12 2009
module \74ls256 (a, \clr* , cp, \e* , \es* , o, \ps* );
input [8:0] a;
input \clr* ;
input cp;
input \e* ;
input \es* ;
www.eeworm.com/read/21695/838793
vhd vhdl.vhd
-- generated by newgenasym Thu Apr 30 11:30:12 2009
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity \74ls256\ is
port (
A: IN STD_LOGIC_VECTOR (8 DOWNTO 0
www.eeworm.com/read/39074/1119629
vhd vhdl.vhd
-- generated by newgenasym Thu Apr 30 11:30:12 2009
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity \74ls256\ is
port (
A: IN STD_LOGIC_VECTOR (8 DOWNTO 0