vhdl.vhd

Cadence16.2完全学习手册

-- generated by newgenasym Thu Apr 30 11:30:12 2009

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74ls256\ is
    port (    
	A:         IN     STD_LOGIC_VECTOR (8 DOWNTO 0);    
	\clr*\:    IN     STD_LOGIC;    
	CP:        IN     STD_LOGIC;    
	\e*\:      IN     STD_LOGIC;    
	\es*\:     IN     STD_LOGIC;    
	O:         OUT    STD_LOGIC_VECTOR (8 DOWNTO 0);    
	\ps*\:     IN     STD_LOGIC);
end \74ls256\;