verilog.v

Cadence16.2完全学习手册

// generated by newgenasym  Thu Apr 30 11:30:12 2009


module \74ls256  (a, \clr* , cp, \e* , \es* , o, \ps* );
    input [8:0] a;
    input \clr* ;
    input cp;
    input \e* ;
    input \es* ;
    output [8:0] o;
    input \ps* ;


    initial
        begin
        end

endmodule