代码搜索：1Hz
找到约 197 项符合「1Hz」的源代码
代码结果 197
www.eeworm.com/read/139899/13122185
v clkdiv1s.v
//-------分频子模块--------//
//输入20MHz，输出1Hz
module clkdiv1s(clkin,clkout);
parameter clk_count_max=20000000-1;// 2^25=33554432
input clkin;
output clkout;
reg clkout;
reg[24:0] clk_count
www.eeworm.com/read/240876/13189759
vhd count60.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count60 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/240876/13189787
vhd count24.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count24 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/325597/13194998
vhd count60.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count60 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/325597/13195027
vhd count24.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count24 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/138605/13228556
vhd count60.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count60 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/138605/13228581
vhd count24.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count24 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/314829/13558207
vhd dividef.vhd
-- 分频电路，平台提供的频率为50MHZ,进行分频，便于观察！
library IEEE; ---get 1HZ
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dividef is
port (
CLK : in std_l
www.eeworm.com/read/310741/13644719
vhd count60.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count60 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/310741/13644727
vhd count24.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count24 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of