dividef.vhd

来自「38译码器的设计」· VHDL 代码 · 共 37 行

-- 分频电路，平台提供的频率为50MHZ,进行分频，便于观察！
library IEEE;   ---get 1HZ 
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dividef is
          port (
                    CLK : in std_logic;         
                    CLK_D:   out std_logic
                   
          );
end entity;

architecture DIVIDE_arch of dividef is
signal COUNT : integer range 0 to 50000000;
begin
  PROCESS(CLK)
       BEGIN
          if clk'event and clk='1' then
                IF COUNT=50000000 then
                    COUNT<=0;
                   ELSE COUNT<=count+1;
                 END IF;
           END IF;        
END PROCESS;

PROCESS(COUNT)
BEGIN
          
                IF COUNT=50000000 THEN   
                    CLK_D<='1';
                   ELSE CLK_D<='0';
                 END IF;
END PROCESS;

end architecture;