代码搜索：1Hz
找到约 197 项符合「1Hz」的源代码
代码结果 197
www.eeworm.com/read/273079/10928454
bak cnt.vhd.bak
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity CNT is
port(
CLKK : IN STD_LOGIC; -- 1Hz
CLK : IN STD_LOGIC;
cout : out STD_LOGIC;
q_bcd :out
www.eeworm.com/read/273079/10928468
vhd cnt.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity CNT is
port(
CLKK : IN STD_LOGIC; -- 1Hz
CLK : IN STD_LOGIC;
cout : out STD_LOGIC;
q_bcd :out
www.eeworm.com/read/416762/11013868
_c timer1._c
#include
#include
#include
#include
//TIMER0 initialize - prescale:8
// WGM: Normal
// desired value: 1Hz
// actual value: 1953.125Hz (99.9%)
voi
www.eeworm.com/read/416762/11013914
c timer1.c
#include
#include
#include
#include
//TIMER0 initialize - prescale:8
// WGM: Normal
// desired value: 1Hz
// actual value: 1953.125Hz (99.9%)
voi
www.eeworm.com/read/323586/13334704
vhd clock.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clock is
Port ( clk : in std_logic; --1Hz
reset : in std_logic; --复位信号
www.eeworm.com/read/475765/6778129
m clex115dt.m
% CLEX115DT.M Create data for processing
% for Example 11.5 in file CLEX95.MAT
% Result has Resolution= 1/NTs= 1Hz; Valid Range is to 64Hz
% (There will be symmetry about 64Hz ie at 64+(64-20)
www.eeworm.com/read/377553/9271625
vhd count60.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count60 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/377553/9271633
vhd count24.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count24 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/164942/10081173
vhd count60.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count60 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of
www.eeworm.com/read/164942/10081181
vhd count24.vhd
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity count24 is
Port(carry: in std_logic;--from 1Hz input clock or the full_index of