cnt.vhd

基于VHDL的8位十进制频率计的详细设计。

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity CNT is
	 port(
		 CLKK : IN STD_LOGIC;  -- 1Hz
		 CLK  : IN STD_LOGIC;
		 cout : out STD_LOGIC;
		 q_bcd :out STD_LOGIC_VECTOR(7 downto 0)
	     );
end CNT;
architecture CNT100 of CNT is
signal DIV2CLK,CNT_EN,RST_CNT : STD_LOGIC;
signal q_tmp :STD_LOGIC_VECTOR(7 downto 0);
begin
PP:   PROCESS( CLKK )
    BEGIN
      IF CLKK'EVENT AND CLKK = '1' THEN  DIV2CLK <= NOT DIV2CLK;
     END IF;
    END PROCESS;
    PROCESS (CLKK, DIV2CLK)
    BEGIN
        IF CLKK='0' AND Div2CLK='0' THEN  RST_CNT <= '1';
        ELSE  RST_CNT <= '0';   
		END IF;
    END PROCESS;
    CNT_EN <= DIV2CLK;
pe:	process(CLK,RST_CNT,CNT_EN)
	begin
		if RST_CNT='1' then 
		q_tmp<=(others=>'0');	
		elsif CLK'event and CLK='1' then
			if CNT_EN='1' then
				if 	q_tmp=99 then
				  q_tmp<=(others=>'0');
				else
			      q_tmp<=q_tmp+1;
				end if;
			end if;
		end if;
	end process;
q_bcd <= q_tmp;
cout <= q_tmp(0) AND q_tmp(1) AND q_tmp(5) AND q_tmp(6);
end ;