代码搜索：1Hz
找到约 197 项符合「1Hz」的源代码
代码结果 197
www.eeworm.com/read/32279/879518
vhd clk_1hz.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_1hz is
port(
clk10k:in std_logic; ------时钟信号10khZ
clk1hz:out std_logic); -----频率信号输出1Hz
www.eeworm.com/read/39267/1122536
vhd clk_1hz.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_1hz is
port(
clk10k:in std_logic; ------时钟信号10khZ
clk1hz:out std_logic); -----频率信号输出1Hz
www.eeworm.com/read/328695/3437097
vhd clk_1hz.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_1hz is
port(
clk10k:in std_logic; ------时钟信号10khZ
clk1hz:out std_logic); -----频率信号输出1Hz
www.eeworm.com/read/392141/8361996
vhd div_clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div_clock is
port(
clk:in std_logic; --系统时钟，选定5MHZ
clk_1hz:out std_logic; --用于时间显示，为1hz
clk_100hz:ou
www.eeworm.com/read/422277/10650496
vhd division.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity division is
port(clk_in:in std_logic; --1MHz
clk_100,clk_5,clk_1:out std_logic); --100Hz,5Hz,1Hz
end
www.eeworm.com/read/159414/10651443
c 24c01.c
#include
#include
#include
//*************************************************
//将2004 年1 月25 日星期日 上午11点10分30 秒的时间写入PCF8563
//以下在PCF8563 的CLKOUT 脚输出1Hz 的方波
//读出
www.eeworm.com/read/394823/7095103
v bell.v
module Bell(Alarm_clock,Set_Hr,Set_Min,Hour,Minute,Second,SetHrkey,
SetMinkey,_1kHz,_500Hz,_1Hz,CtrlBell);
output Alarm_clock;
output [7:0]Set_Hr,Set_Min;
wire[7:0]Set_Hr,Set_Min;
wire Ala
www.eeworm.com/read/394823/7095222
v bell.v
module Bell(Alarm_clock,Set_Hr,Set_Min,Hour,Minute,Second,SetHrkey,
SetMinkey,_1kHz,_500Hz,_1Hz,CtrlBell);
output Alarm_clock;
output [7:0]Set_Hr,Set_Min;
wire[7:0]Set_Hr,Set_Min;
wire Ala
www.eeworm.com/read/394823/7095357
v bell.v
module Bell(Alarm_clock,Set_Hr,Set_Min,Hour,Minute,Second,SetHrkey,
SetMinkey,_1kHz,_500Hz,_1Hz,CtrlBell);
output Alarm_clock;
output [7:0]Set_Hr,Set_Min;
wire[7:0]Set_Hr,Set_Min;
wire Ala
www.eeworm.com/read/214738/15090426
vhd main.vhd
--
-- File: main.vhd
-- 主文件，将各部分组合起来
-- 1024HZ->16HZ->1HZ
library IEEE;
use IEEE.std_logic_1164.all;
entity main is
port (
clk1k: in STD_LOGIC;
reset: in STD_LOGIC;
led: out S