main.vhd

来自「交通灯信号控制器」· VHDL 代码 · 共 95 行

--
--  File: main.vhd
--  主文件，将各部分组合起来 
--  1024HZ->16HZ->1HZ

library IEEE;
use IEEE.std_logic_1164.all;

entity main is
	port (
		clk1k: in STD_LOGIC;
		reset: in STD_LOGIC;
		led: out STD_LOGIC_VECTOR (6 downto 0);
		col: out STD_LOGIC_VECTOR (3 downto 0);
		RedA: out STD_LOGIC;
		RedB: out STD_LOGIC;
		GreenA: out STD_LOGIC;
		GreenB: out STD_LOGIC;
		YellowA: out STD_LOGIC;
		YellowB: out STD_LOGIC
	);
end main;



architecture rtl of main is	

component fdiv32 is	 	
	port ( 	    
		clkin: in STD_LOGIC;
		clkout: out STD_LOGIC
	);
end component fdiv32; 

component fdiv8 is	 	
	port ( 	    
		clkin: in STD_LOGIC;
		clkout: out STD_LOGIC
	);
end component fdiv8;

component controller is
	port (
		clk1: in STD_LOGIC;
		reset: in STD_LOGIC;
		RedA: out STD_LOGIC;
		RedB: out STD_LOGIC;
		GreenA: out STD_LOGIC;
		GreenB: out STD_LOGIC;
		YellowA: out STD_LOGIC;
		YellowB: out STD_LOGIC;
		NumA: out INTEGER range 0 to 40;
		NumB: out INTEGER range 0 to 40
	);
end component controller;  

component separate is
	port (
		clk10: in STD_LOGIC;
		NumIn: in INTEGER range 0 to 40;
		NumOutH: out INTEGER range 0 to 9;
		NumOutL: out INTEGER range 0 to 9
	);
end component separate;

component display is
	port (
        reset: in STD_LOGIC;
		clk1k: in STD_LOGIC;
		col: out STD_LOGIC_VECTOR (3 downto 0);
		led: out STD_LOGIC_VECTOR (6 downto 0);
		data1: in INTEGER range 0 to 9;
		data2: in INTEGER range 0 to 9;
		data3: in INTEGER range 0 to 9;
		data4: in INTEGER range 0 to 9
	);
end component display;

signal clk10:STD_LOGIC;
signal clk1:STD_LOGIC;
signal NumA,NumB:integer range 0 to 40;
signal data1,data2,data3,data4:integer range 0 to 9;
begin 
	p1:fdiv32 port map(clkin=>clk1k,clkout=>clk10);
	p2:fdiv8  port map(clkin=>clk10,clkout=>clk1);
	p3:controller port map(clk1=>clk1,reset=>reset,RedA=>RedA,RedB=>RedB,
                           GreenA=>GreenA,GreenB=>GreenB,YellowA=>YellowA,
						   YellowB=>YellowB,NumA=>NumA,NumB=>NumB);
	p4:separate	port map(clk10=>clk10,NumIn=>NumA,NumOutH=>data1,NumOutL=>data2);
	p5:separate	port map(clk10=>clk10,NumIn=>NumB,NumOutH=>data3,NumOutL=>data4);
	p6:display	port map(reset=>reset,clk1k=>clk1k,col=>col,led=>led,data1=>data1,data2=>data2,
	                     data3=>data3,data4=>data4);

end rtl;