代码搜索：1Hz
找到约 197 项符合「1Hz」的源代码
代码结果 197
www.eeworm.com/read/404220/11489897
asv doppler_psd.asv
clear all
N = 100;
fm = 128; %unit: 1Hz
deltaf = 2*fm/(N-1);
T = 1/deltaf;
sf0 = 1.5/(pi*fm);
for n = 1:(N-2)/2
sf(n) = 1.5/(pi*fm*sqrt(1-(n*deltaf/fm)^2));
end
classicf = [flipl
www.eeworm.com/read/108782/15575583
vhd control_produce.vhd
--控制信号产生器
--
--端口说明
--reset : 复位信号reset = '1'时复位,清零
--clk_in : 脉冲输入1Hz
--control : 控制信号输出
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY control_
www.eeworm.com/read/281861/9128656
vhd divider_1m.vhd
Library IEEE ;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY divider_1m IS
PORT(clk : IN STD_LOGIC; --全局时钟
clk1s : OUT STD_LOGIC); --频率为1HZ的低占空比时钟
END divider_1
www.eeworm.com/read/366374/9819646
asv homework_one213.asv
%题目2-1-3 演示程序：f=1Hz，初始相位delta=0，抽样间隔T=0.1秒，序列长length=10
clc;clf;
f=0.5; delta=0; T=0.1; N=10; %设置参数
t=0:pi/30:N*T; %设置步长
n=0:N-1;
www.eeworm.com/read/366374/9819653
m homework_one214.m
%题目2-1-4 演示程序：f=1Hz，初始相位delta=0，抽样间隔T=0.1秒，序列长length=10
clc;clf;
f=1; delta=0; T=0.1; N=10; %设置参数
t=0:0.001:N*T; %设置步长
n=0:N-1;
www.eeworm.com/read/366374/9819659
m homework_one213.m
%题目2-1-3 演示程序：f=1Hz，初始相位delta=0，抽样间隔T=0.1秒，序列长length=10
clc;clf;
f=1; delta=0; T=0.1; N=10; %设置参数
t=0:0.001:N*T; %设置步长
n=0:N-1;
www.eeworm.com/read/470983/6902393
vhd clk_1hz.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_1hz is
port(
clk10k:in std_logic; ------时钟信号10khZ
clk1hz:out std_logic); -----频率信号输出1Hz
www.eeworm.com/read/307021/13732881
vhd divider_1m.vhd
Library IEEE ;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY divider_1m IS
PORT(clk : IN STD_LOGIC; --全局时钟
clk1s : OUT STD_LOGIC); --频率为1HZ的低占空比时钟
END divider_1
www.eeworm.com/read/214738/15090417
vhd controller.vhd
--
-- File: controller.vhd
-- 控制模块：输入clk1为1HZ时钟信号,reset,输出为LED信号和倒计时值
library IEEE;
use IEEE.std_logic_1164.all;
entity controller is
port (
clk1: in STD_LOGIC;
reset: in STD_LOGIC;
www.eeworm.com/read/17631/743970
vhd clk_1hz.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_1hz is
port(
clk10k:in std_logic; ------时钟信号10khZ
clk1hz:out std_logic); -----频率信号输出1Hz