divider_1m.vhd

这是一些经典的vhdl example

Library IEEE ;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY divider_1m IS
	PORT(clk 				: IN STD_LOGIC;		--全局时钟
		 clk1s				: OUT STD_LOGIC);   --频率为1HZ的低占空比时钟
END divider_1m;
ARCHITECTURE rtl OF divider_1m IS
	--用于仿真
	SIGNAL cnt				: INTEGER RANGE 0 TO 1;	
	--用于实际下载
	--SIGNAL cnt				: INTEGER RANGE 0 TO 999999;
BEGIN
	PROCESS(clk)
	BEGIN
		IF(clk'event AND clk='1')THEN
			IF(cnt=cnt'high)THEN 
				cnt <= 0;
				--寄存器输出译码
				clk1s <= '1';
			ELSE
				cnt <= cnt +1;
				--寄存器输出译码
				clk1s <= '0';
			END IF;
		END IF;
	END PROCESS;
END rtl;