control_produce.vhd

用VHDL语言编写

--控制信号产生器
--
--端口说明
	--reset		: 复位信号reset = '1'时复位,清零 
	--clk_in	: 脉冲输入1Hz
	--control	: 控制信号输出
	
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY control_produce IS
	PORT(
		clk_in		: IN	STD_LOGIC;
		reset		: IN	STD_LOGIC;
		control		: OUT	STD_LOGIC);
END control_produce;

ARCHITECTURE control_produce_run OF control_produce IS
	SIGNAL clk_10 : STD_LOGIC;
	SIGNAL clk_60 : STD_LOGIC;
BEGIN
	PROCESS (reset,clk_in)
		VARIABLE mid : STD_LOGIC_VECTOR(5 DOWNTO 0);
	BEGIN
		IF (reset = '1') THEN
		    mid := "000000";
		ELSIF (clk_in'EVENT AND clk_in = '1') THEN
		    --59 = B"111011"
		    IF (mid = "111011") THEN
		    	mid := "000000";
		    ELSE
		    	mid := mid+'1';
		    END IF;
		END IF;
		
		--59 = B"111011"
		--9 = B"001001"
		clk_10 <= (NOT mid(5)) AND (NOT mid(4)) AND mid(3) 
				  AND (NOT mid(2)) AND (NOT mid(1)) AND mid(0);
		clk_60 <= mid(5) AND mid(4) AND mid(3) AND (NOT mid(2))
				  AND mid(1) AND mid(0);
	END PROCESS;
	
	control <= clk_10 OR clk_60;
END control_produce_run;