代码搜索：电路图纸
找到约 10,000 项符合「电路图纸」的源代码
代码结果 10,000
www.eeworm.com/read/272558/10953369
c main.c
/*******************************************************************************
*File: Main.c
*功能: 使用PWM6输出PWM信号,通过滤波电路实现DAC转换.由KEY1控制PWM占空比,每按一次
* 按键将会改变一次PWM的占空比
**************************
www.eeworm.com/read/271091/11007712
vhd cmi_decoder.vhd
--CMI译码电路
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CMI_DECODER IS
PORT(clk:IN STD_LOGIC;
deco_in:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
deco_out:OUT STD_LOGIC);
END CMI_D
www.eeworm.com/read/460064/7258360
map putpwm.map
CodeVisionAVR C Compiler V1.25.6 Standard
(C) Copyright 1998-2007 Pavel Haiduc, HP InfoTech s.r.l.
http://www.hpinfotech.com
File: C:\Documents and Settings\Administrator\桌面\可变脉宽输出试验(舵机控制)\源码和电路\
www.eeworm.com/read/459164/7279416
vhd receiver.vhd
--异步接收电路VHDL程序。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity receiver is
port (rst,clk,rxd,ERBF : in std_logic ;
dout : out std_logic_vector (7 downto 0) ;
www.eeworm.com/read/442635/7648601
uv2 temperature_humidity_constant_system.uv2
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (Target 1), 0x0000 // Tools: 'MCS-51'
Group (Source Group 1)
File 1,2,
www.eeworm.com/read/442635/7648602
bak temperature_humidity_constant_system_uv2.bak
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (Target 1), 0x0000 // Tools: 'MCS-51'
Group (Source Group 1)
File 1,2,
www.eeworm.com/read/199292/7869200
vhd xskz.vhd
--显示控制电路的VHDL源程序
--XSKZ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY XSKZ IS
PORT(CLK:IN STD_LOGIC;
CLR:IN STD_LOGIC;
SET:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
LE
www.eeworm.com/read/197218/8011449
txt readme.txt
本系统是用AT89C2051单片机组成的无线电源控制系统，可以用在家庭、办公室、会议室等，具体内容请看电路和源代码！
www.eeworm.com/read/332506/12751749
asm t138.asm
;T138.asm
;地址译码电路设计实验
;****************根据查看端口资源修改下列符号值*******************
IOY0 EQU 9C00H ;片选IOY0对应的端口始地址
;*****************************************************************
www.eeworm.com/read/314829/13558207
vhd dividef.vhd
-- 分频电路，平台提供的频率为50MHZ,进行分频，便于观察！
library IEEE; ---get 1HZ
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dividef is
port (
CLK : in std_l