cmi_decoder.vhd

伪随机序列码发生器及基带传输CMI码编、译码的VHDL语言实现

--CMI译码电路
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CMI_DECODER IS
  PORT(clk:IN STD_LOGIC;
       deco_in:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
       deco_out:OUT STD_LOGIC);
END CMI_DECODER;

ARCHITECTURE RTL OF CMI_DECODER IS
  SIGNAL sig:STD_LOGIC;
  BEGIN
  PROCESS(clk,deco_in)
  BEGIN
    IF(clk'EVENT AND clk='1') THEN
      IF deco_in="11" OR deco_in="00" THEN
        deco_out<='1';
      ELSIF deco_in="01" OR deco_in="10" THEN
        deco_out<='0';
      END IF;
    END IF;
  END PROCESS;
END RTL;