代码搜索：时钟提取

找到约 10,000 项符合「时钟提取」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/32279/880598

vhd jiao_tong.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jiao_tong is port(clk:in std_logic;----20mhz晶振时钟 jin:in std_logic;----禁止通行信号 scan:out std_logic_vecto
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www.eeworm.com/read/32279/880976

vhd jp4x4_1.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jp4x4_1 is port(clk:in std_logic;------扫描时钟信号 start:in std_logic;----开始信号，高电平有效 kbcol:in std_logic_ve
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www.eeworm.com/read/32279/880986

vhd ping_pang.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ping_pang is port(clk1khz:in std_logic;------1khz时钟信号 rst:in std_logic;----------系统复位 af,aj:in std_lo
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www.eeworm.com/read/32279/881782

vhd cymometer.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cymometer is port(sysclk:in std_logic;----20mhz 时钟输入 clkin:in std_logic;-----待测频率信号输入 seg7:out std_lo
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www.eeworm.com/read/32279/882720

vhd maichong.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity maichong is port(clk:in std_logic;-----时钟 clr:in std_logic;-----清零 q0,q1,q2:out std_logic);----脉冲输出
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www.eeworm.com/read/32279/883521

vhd div5_1.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity div5_1 is port(clk:in std_logic;-------时钟 div5:buffer std_logic);----输出5分频信号 end; architecture one of div
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www.eeworm.com/read/32279/884189

vhd div5.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity div5 is generic(n:integer:=5); port(clk:in std_logic;-------时钟 div5:out std_logic);----输出5分频信号 end; arch
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www.eeworm.com/read/32279/884245

vhd div_half.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity div_half is generic(n:integer:=2);--------n为分频系数的整数部分+1 port(clk:in std_logic;--------时钟信号 div:out std_lo
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www.eeworm.com/read/32279/884306

vhd div6.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity div6 is port(clk:in std_logic;--------时钟 div6:out std_logic);----输出6分频信号 end; architecture one of div6 is
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www.eeworm.com/read/32279/885593

vhd div7.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity div7 is port(clk:in std_logic;--------时钟 div7:out std_logic);----输出7分频信号 end; architecture one of div7 is
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