div_half.vhd

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div_half is 
generic(n:integer:=2);--------n为分频系数的整数部分+1
port(clk:in std_logic;--------时钟信号
     div:out std_logic);------输出分频信号
end;
architecture one of div_half is
	signal count:integer:=0;--------计数器
	signal clk_temp1:std_logic;-----脉冲控制端1
	signal clk_temp2:std_logic;-----脉冲控制端2
	signal clk_temp3:std_logic;-----脉冲控制端3
begin
	clk_temp1<=clk xor clk_temp2;
process(clk_temp1)-----------------------模n的减法计数器
begin
if clk_temp1'event and clk_temp1='1' then
	if count=0 then count<=n-1;
	    clk_temp3<='1';
	    div<='1';
	else
		count<=count-1;
		clk_temp3<='0';
		div<='0';
	end if;
end if;
end process;
process(clk_temp3)------------------------2分频电路
begin
	if clk_temp3'event and clk_temp3='1' then
		clk_temp2<=not clk_temp2;
	end if;
end process;
end;