div6.vhd

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div6 is
port(clk:in std_logic;--------时钟
     div6:out std_logic);----输出6分频信号
end;
architecture one of div6 is
	signal cnt:std_logic_vector(2 downto 0);
	signal clk_temp:std_logic;
	constant m:integer:=5;-----控制计数器的常量,m=N-1
begin
process(clk)
begin
if clk'event and clk='1' then
	if cnt=m then
	    clk_temp<='1'; 
	    cnt<="000";
	else 
	    cnt<=cnt+1; 
	    clk_temp<='0';
	end if;
end if;
end process;
div6<=clk_temp;
end;