代码搜索：废墨清零
找到约 859 项符合「废墨清零」的源代码
代码结果 859
www.eeworm.com/read/39267/1124955
vhd clock_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock_1 is
port(clk:in std_logic;----时钟输入 1khz
clr:in std_logic;----清零
en:in std_logic;-----暂停
www.eeworm.com/read/39267/1126458
vhd xl_generate.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xl_generate is
port(clk:in std_logic;-----时钟
clr:in std_logic;-----清零
dout:out std_logic);----输出端
en
www.eeworm.com/read/39267/1127008
vhd piso4.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity piso4 is
port(clk:in std_logic;----时钟
clr:in std_logic;----清零
din:in std_logic_vector(3 downto 0);---
www.eeworm.com/read/39267/1127728
vhd lifo_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lifo_1 is
port(clr:in std_logic;------清零信号
push:in std_logic;-----压栈
pop:in std_logic;------出栈
www.eeworm.com/read/39267/1128744
vhd lifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lifo is
port(clr:in std_logic;--------清零信号
push:in std_logic;-------压栈信号
pop:in std_logic;--------出栈信
www.eeworm.com/read/249482/4450247
dat funtc42.dat
函数名称: clearerr
函数原型: void clearerr(FILE * fp);
函数功能: 清除文件指针错误指示器,将文件出错标志清零.
函数返回: 无.
函数说明: fp 文件的流指针
所属文件:
www.eeworm.com/read/328695/3437713
vhd clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port(clk:in std_logic;-----时钟输入 20mhz
clr:in std_logic;-----清零信号
en:in std_logic;------暂停信号
www.eeworm.com/read/328695/3438096
vhd clock_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock_1 is
port(clk:in std_logic;----时钟输入 1khz
clr:in std_logic;----清零
en:in std_logic;-----暂停
www.eeworm.com/read/328695/3438909
vhd xl_generate.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xl_generate is
port(clk:in std_logic;-----时钟
clr:in std_logic;-----清零
dout:out std_logic);----输出端
en
www.eeworm.com/read/328695/3439199
vhd piso4.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity piso4 is
port(clk:in std_logic;----时钟
clr:in std_logic;----清零
din:in std_logic_vector(3 downto 0);---