xl_generate.vhd

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xl_generate is
port(clk:in std_logic;-----时钟
     clr:in std_logic;-----清零
     dout:out std_logic);----输出端
end;
architecture one of xl_generate is
	signal reg:std_logic_vector(7 downto 0);
begin
process(clk,clr)
begin
if clk'event and clk='1' then
	if clr='1' then 
		dout<='0';
		reg<="10110101";
	else 
		dout<=reg(7);---------------循环输出reg中的序列
		reg<=reg(6 downto 0)& reg(7);
	end if;
end if;
end process;
end;