代码搜索：光子计数
找到约 7,260 项符合「光子计数」的源代码
代码结果 7,260
www.eeworm.com/read/452719/7434142
ms7 6.20 置零法计数器.ms7
www.eeworm.com/read/452719/7434158
ms7 6.21 置数法计数器.ms7
www.eeworm.com/read/452341/7441862
asm at24c02的开机计数器.asm
;=================================================
; at24c02的开机计数器，系统复位一次数码管加1
; 按SW2 复位
; 24c02 储存计数器程序、断电数据保持、
; 每次开机数码管显示加 1
;=================================================
;
;====
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txt 计数器：std_logic_unsigned的用法.txt
-- This example shows the use of the package 'std_logic_unsigned' .
-- The minus operator '-' is overloaded by this package, thereby allowing an integer to be subracted from a std_logic_vector.
--
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txt 计数器：std_logic_unsigned的用法.txt
-- This example shows the use of the package 'std_logic_unsigned' .
-- The minus operator '-' is overloaded by this package, thereby allowing an integer to be subracted from a std_logic_vector.
--
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txt 用状态机实现的计数器.txt
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTIT
www.eeworm.com/read/197597/7984713
txt 计数器：std_logic_unsigned的用法.txt
-- This example shows the use of the package 'std_logic_unsigned' .
-- The minus operator '-' is overloaded by this package, thereby allowing an integer to be subracted from a std_logic_vector.
--
www.eeworm.com/read/197597/7984828
vhd 用状态机实现的计数器.vhd
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTIT
www.eeworm.com/read/196997/8036559
txt 4位10进制计数器vhdl程序.txt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( clk : in std_logic;
reset : in std_logic;
www.eeworm.com/read/296501/8098358