计数器：std_logic_unsigned的用法.txt

很好的VHDL源码,里面有不少实用的实例!

-- This example shows the use of the package 'std_logic_unsigned' . 
-- The minus operator '-' is overloaded by this package, thereby allowing an integer to be subracted from a std_logic_vector. 
-- dowload from: www.fpga.com.cn & www.pld.com.cn

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY pldcntr8 IS 
   PORT (clk, load : IN Std_logic; 
         datain : IN Std_logic_vector(7 DOWNTO 0);
         q : OUT Std_logic_vector(7 DOWNTO 0);
         tc : OUT Std_logic);
END pldcntr8;

ARCHITECTURE using_std_logic OF pldcntr8 IS

   SIGNAL count : Std_logic_vector(7 DOWNTO 0);

BEGIN

   PROCESS
   BEGIN
      WAIT UNTIL rising_edge(clk);
      IF load = '1' THEN
          count <= datain;
      ELSE
          count <= count - 1;
      END IF;
   END PROCESS;

   tc <= '1' WHEN count = "00000000" ELSE '0';
   q <= count;

END using_std_logic;