4位10进制计数器vhdl程序.txt

来自「这是老师给但计数器程序」· 文本 代码 · 共 43 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
   Port ( clk : in std_logic;
          reset : in std_logic;
          updn : in std_logic;
          q0,q1,q2,q3: out std_logic;
          q : out std_logic_vector(3 downto 0)
         );
end counter;
architecture Behavioral of counter is
   signal qn : std_logic_vector(3 downto 0);
begin
q0 <= qn(0);
q1 <= qn(1);
q2 <= qn(2);
q3 <= qn(3);
process(clk,reset,updn)
begin
if (reset='1') then
qn <= (others=>'0');
 elsif (clk'event and clk='1')then
  if (updn='1') then
     if (qn=9) then
        qn<="0000";
     else
        qn <= qn+1;
     end if;
  else
     if (qn=0) then
       qn<="1001";
     else
        qn <= qn-1;
     end if;
  end if;
end if;
end process;
q<=qn;
end Behavioral;