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VHDL/FPGA/Verilog Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。
Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。
VHDL/FPGA/Verilog Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。
Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。
系统设计方案 This text surrounds the development of the electric power SCADA system exactly, aiming at the presen
This text surrounds the development of the electric power SCADA system exactly, aiming at the present condition of the our country electric power charged barbed wire net currently, according to the oneself at the e- lectric power protect the profession after the electricity in seven years of develop ...
其他数据库 student select course system,powerbuilder做的
student select course system,powerbuilder做的，很容易实现 ,不会有人上载了吧
单片机开发 Chinese Font display in embedded system
Chinese Font display in embedded system
其他 check and alarm system
check and alarm system
其他书籍 A book describle in detail about the system security and usability technology. It is a system book o
A book describle in detail about the system security and usability technology. It is a system book on security.
Java编程 A part public bus simulation system, mainly about map design, java file, groupwork, helpful to the b
A part public bus simulation system, mainly about map design, java file, groupwork, helpful to the beginners
人工智能/神经网络 属性约简程序： 1将roughset数据库附加到SQLServer2000数据库中 2 在system.ini中设置SQLServer2000服务器ip,若在本地
属性约简程序：
1将roughset数据库附加到SQLServer2000数据库中
2 在system.ini中设置SQLServer2000服务器ip,若在本地，则不必设置
3 在CTR表中输入决策表
4 启动roughset_getreduce.exe求约简和规则.
系统设计方案 经典计算机体系结构RISC8的源代码（Verilog）
经典计算机体系结构RISC8的源代码（Verilog），包括CPU、内存、寄存器等的实现