搜索：system verilog - 虫虫下载站

VHDL/FPGA/Verilog 实现乒乓缓存

实现乒乓缓存，用verilog语言编写！

https://www.eeworm.com/dl/663/306604.html

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缓存

通讯/手机编程  96位矩阵循环乘法

96位矩阵循环乘法，verilog实现，

https://www.eeworm.com/dl/527/329158.html

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矩阵循环乘法

VHDL/FPGA/Verilog LCD显示

LCD显示，用verilog写的，quartusII

https://www.eeworm.com/dl/663/427615.html

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LCD

嵌入式/单片机编程  SPI接口代码

SPI接口代码，非常精简，verilog版本。

https://www.eeworm.com/dl/647/434614.html

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SPI 接口代码

技术资料  fir滤波器

简单fir滤波器程序verilog

https://www.eeworm.com/dl/872323.html

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滤波器

技术资料  afaf

数字信号系统verilog实现

https://www.eeworm.com/dl/973928.html

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afaf

其他  The JICQ is the bureau area which JAVA writes according to "Customer s Machine/Server"(C/S) mode mes

The JICQ is the bureau area which JAVA writes according to "Customer s Machine/Server"(C/S) mode message solid hour correspond by letter tool system, the system adopted the SQL Server2000 of Microsoft company as a backstage database, the system passes a JDBC interview database. The system is divided ...

https://www.eeworm.com/dl/534/164209.html

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according Customer Machine Server

技术资料  重复控制理论在无速度传感器永磁同步电机自学习控制中的应用

This study presents a solution to control a PMSM without sensors. The control method is the presented superposition principle. This method of sensorless theory is very simple to compute estimated angle. Therefore, computing time to estimate angle is shorter than other sensorless methods. The use of ...

https://www.eeworm.com/dl/902294.html

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sensorless control system

技术书籍  SystemVerilog for Design

·SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling ver

https://www.eeworm.com/dl/537/15695.html

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nbsp SystemVerilog Design for

技术资料  SystemVerilog for Design

·SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling ver

https://www.eeworm.com/dl/879635.html

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nbsp SystemVerilog Design

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