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uCOS this code is a simulator to simulate the paging system such as first come first service. the comment
this code is a simulator to simulate the paging system such as first come first service. the comment in this code can help you to run it.
其他 Verilog编写的M序列发生器
Verilog编写的M序列发生器，希望能对大家带来帮助。
通讯编程文档 A power control algorithm for 3G wcdma system, paper by Loutfi Nuaymi,
A power control algorithm for 3G wcdma system, paper by Loutfi Nuaymi,
其他书籍 Verilog的学习资料
Verilog的学习资料，可编程器件fpga的开发语言，有重点介绍Verilog的关键语法
uCOS Porting UCOS-II v2.0 to S3C2410 with File System v1.34 and RAM driver
Porting UCOS-II v2.0 to S3C2410 with File System v1.34 and RAM driver
其他 verilog 实现的jtag ip模块 包括了测试程序
verilog 实现的jtag ip模块
包括了测试程序
微处理器开发 Use the verilog language write a MIPS CPU code, and have additional instruction, for example: select
Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction.
The code has contain combination circuit and sequenial circuit.
CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.
微处理器开发 The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) de
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and ...
VHDL/FPGA/Verilog PLD与8051接口的参考设计 Xilinx提供的verilog源代码
PLD与8051接口的参考设计 Xilinx提供的verilog源代码
人工智能/神经网络 Fuzzy logic system VC classes
Fuzzy logic system VC classes